ARQUIMEA, we are a technology company operating globally and providing innovate solutions and products in highly demanding sectors.

Our areas of activity are Aerospace, Defense & Security, Big Science, Biotechnology and Fintech.

Technical Requirements:

•   Experience in automated synthesis and timing driven place and route of RTL blocks

•   Experience in automated clock tree synthesis, design optimization, and design cycle time reduction

•   Experience in floor planning, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff

• Good knowledge of back-end tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation, e.g.: Genus, Innovus, Tempus, APRISA, Catapult, etc

Required skills, experience and candidate profile:

• Telecommunications engineering, electronic engineering or equivalent

• Master in micro-electronics or applicable experience in the field

• Experience with scripting in python, TCL, Bash, etc

• +5 years of experience in back-end ASIC design

The position is located at our headquarters in Madrid, at Calle Serrano Galvache, 56.

We're looking for curious, creative, tenacious and collaborative people, eager to do things and unafraid to tackle challenges in order to contribute to improving the society in wich we live.

Think Big, Do the Job & Enjoy Life

At ARQUIMEA, we value diversity and inclusion. We do not discriminate on the basis of race, color, religion, gender, sexual orientation, gender identity, national origin, age, disability, or other protected factors by law. All candidates will be considered equally based on their skills and experience